What is RISC-V

RISC-V is an open standard instruction set architecture (ISA) that follows the principles of reduced instruction set computer (RISC) design. Unlike other ISAs, RISC-V is available under royalty-free open-source licenses. It has gained support from various companies and has compatible hardware and operating systems. The architecture is designed to simplify CPU implementation, with specific features like simplified bit field locations and fixed positions for immediate values. The instruction set is versatile, with a fixed length of 32-bit instructions and the ability to support variable-length extensions. It caters to different systems, ranging from small embedded devices to supercomputers and parallel computers. While there is a 128-bit address space variant, it is not yet widely used due to limited practical experience. The project started at the University of California, Berkeley, but now has contributions from volunteers outside the university. The RISC-V instruction set is intended for practical use, and the user space and privileged ISAs have been frozen for software and hardware development

About SoC42

To reduce dependence on imported chips and hold the IP in India iCreate developed a ‘System on Chip’ that can replace a motor controller, a vehicle control unit, and a battery thermal management system – in a tiny QFN chip.

About Contest

RISC-V Contest is organised by iCreate under the banner of EVangelise '23. This event will enable startups, businesses, students and technology enthusiasts to build solutions for the electric vehicle industry like motor controllers, BMS, telematics with NavIC, etc. by using RISC-V architecture-based Shakti, VEGA, SoC42 and other similar platforms.

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Cash Prizes

RISC-V will have up to 10 finalists, each with a cash prize of INR 1 Lakh.

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